Transistors

ABSTRACT

Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor. The first and second transistors have first and second active regions, respectively. Dielectric features are associated with the first active region and break up the first active region. The second active region is not broken up to the same extent as the first active region. Some embodiments include methods of forming transistors. Active areas of first and second transistors are formed. The active area of the first transistor is wider than the active area of the second transistor. Dielectric features are formed in the active area of the first transistor. The active area of the first transistor is broken up to a different extent than the active area of the second transistor. The active areas of the first and second transistors are simultaneously doped.

TECHNICAL FIELD

Integrated circuitry and methods of forming transistors.

BACKGROUND

Transistors, such as field effect transistors (FETs), having highbreakdown voltages (e.g., above about 15 volts, and in some applicationsto about 80 volts or greater) are used in various integrated circuitapplications. Transistors having high breakdown voltages may be referredto as high-voltage transistors, meaning that the transistors areconfigured to tolerate high voltages (e.g., above 15 volts).

One technique for creating a high-voltage transistor uses alightly-doped diffusion region (LDD region) between the drain and gateof the transistor. This region is an active area of the transistor, andis sometimes referred to as a drain extension region. One class ofdevices utilizing LDD regions are Reduced Surface Field Devices (RESURF)devices.

High-voltage transistors may be configured with different drivecurrents. For instance, wide transistors may have higher drive currentsthan narrow transistors.

The active area of a high-voltage transistor is doped to form the LDDregion, and there will be an optimum doping that will achieve a desiredbreakdown characteristic. Transistors having different drive currentsmay have different optimum doping concentrations relative to one another(e.g., wider transistors may have a different optimum dopingconcentration than narrower transistors), which can be problematicduring fabrication of the transistors. Specifically, it can beproblematic to utilize multiple doping steps during fabrication ofhigh-voltage transistors in that multiple doping steps add process stepsand thus may increase fabrication costs as compared to a single dopingstep. It would be desirable to develop alternative transistorstructures, and methods of their formation, which enable a single dopingstep to appropriately dope multiple high-voltage transistors havingdifferent drive currents.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagrammatic view of circuitry that may be on an integratedcircuit chip, and of circuitry that may be coupled with the circuitry onthe chip, in an example embodiment.

FIG. 2 is a diagrammatic top view of an example embodiment high-voltagetransistor. FIG. 2A is a diagrammatic cross-sectional side view alongthe line 2A-2A of FIG. 2.

FIG. 3 is graphical illustration of an example embodiment relationshipbetween breakdown voltage drain-source-substrate at ground (BV_(dss))and active area implant dose for a high-voltage transistor.

FIG. 4 is a simplified graphical illustration of a suitable dopantwindow for a achieving a BV_(dss) within a desired range relative to therelationship shown in FIG. 3.

FIG. 5 is a graphical illustration of suitable dopant windows forachieving BV_(dss) within desired ranges for two high-voltagetransistors that are of differing widths relative to one another.

FIG. 6 is a diagrammatic top view of a portion of an example embodimentintegrated circuit region comprising two high-voltage transistors thatare of differing widths relative to one another.

FIG. 7 is a graphical illustration of suitable dopant windows forachieving BV_(dss) within desired ranges for four high-voltagetransistors that are of differing widths relative to one another.

FIG. 8 is a diagrammatic top view of a portion of an example embodimentintegrated circuit region comprising four high-voltage transistors thatare of differing widths relative to one another.

FIG. 9 is a diagrammatic top view of an example embodiment high-voltagetransistor modified with dielectric features within an active area ofthe device. FIG. 9A is a diagrammatic cross-sectional side view alongthe line 9A-9A of FIG. 9.

FIG. 10 is a graphical illustration of an example embodiment effect ofthe modification of FIG. 9 on a suitable dopant window for achievingBV_(dss) within a desired range for a high-voltage transistor.

FIG. 11 is a graphical illustration of suitable dopant windows forachieving BV_(dss) within desired ranges for four high-voltagetransistors that are of differing widths relative to one another aftermodification of some of the devices with dielectric features analogousto those shown in FIG. 9.

FIG. 12 is a diagrammatic top view of a portion of an example embodimentintegrated circuit region comprising four high-voltage transistors thatare of differing widths relative to one another; with various of thehigh-voltage transistors comprising dielectric features within activeareas of the devices.

FIG. 13 is a diagrammatic top view of another example embodimenthigh-voltage transistor modified with dielectric features within anactive area of the device.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

Some embodiments include methods for altering the optimum LDD implantdose of a high-voltage transistor while substantially maintaining thedrive current of the transistor. Such methods may be utilized duringfabrication of multiple high-voltage transistors of different widths sothat a common LDD implant may be utilized for forming active regions ofall of the high-voltage transistors. In some embodiments, a method foraltering the optimum LDD implant dose of a high-voltage transistorcomprises breaking up an active region of the transistor with aplurality of dielectric features. Example embodiments are describedbelow with reference to FIGS. 1-13.

Referring to FIG. 1, an example embodiment integrated circuit chip 2 isillustrated to show an example application of high-voltage circuitry.Specifically, a high-voltage source 3 provides power to the chip. Thehigh-voltage source is diagrammatically illustrated to be external ofthe chip, and may be electrically connected to the chip through anysuitable arrangement, such as, for example, wires, pins, etc. Althoughthe high-voltage source is shown external of the chip, it is to beunderstood that in some applications the source may be on the chipitself; and in such applications the high voltage source may comprisepump circuitry utilizing high voltage transistors.

The integrated circuit chip 2 comprises a first level of circuitry 4which is directly electrically coupled to the high-voltage source. Suchfirst level of circuitry comprises high-voltage circuitry, such as, forexample, high-voltage transistors. The high-voltage transistors may havehigh breakdown voltages (for instance, about 15 volts or greater) inorder to tolerate the high voltages that such transistors may be exposedto.

The integrated circuit chip 2 comprises a second level of circuitry 6which is coupled to the first level of circuitry 4. The second level ofcircuitry may be memory circuitry, logic circuitry, etc., and the firstlevel of circuitry may be utilized to transform the powercharacteristics of the high-voltage source into characteristics suitablefor driving and/or otherwise operating the second level of circuitry.For instance, in some applications the second level of circuitry maycomprise flash memory (for instance, NAND memory) and the first level ofcircuitry may be utilized to provide power for a block erase of theflash memory and/or for reading and programming of the memory.

It can be desired that the first level of circuitry comprise numeroushigh-voltage transistors, with some of the transistors having higherdrive currents than others (for instance, with some of the transistorsbeing wider than others). As discussed above in the “Background” sectionof this disclosure, it can be difficult to fabricate multiplehigh-voltage transistors of differing drive currents due to thedifferent LDD doses that may be required.

FIGS. 2 and 2A show an example embodiment high-voltage transistor 10.The transistor comprises n-type doped LDD regions 14 extending into ap-type doped semiconductor substrate 12. The substrate 12 may comprise,consist essentially of, or consist of monocrystalline silicon in someembodiments. In the shown embodiment, the substrate is supported by anelectrically insulative material 10. Such material 10 may be anysuitable composition or combination of compositions, and may, forexample, comprise, consist essentially of, or consist of silicondioxide. The shown embodiment may be an example of asilicon-on-insulator (SOI) configuration. In other embodiments, otherconfigurations may be utilized; for example, high-voltage transistorsmay comprise doped regions extending into bulk semiconductor materialrather than in SOI constructions.

The LDD regions 14 extend between a channel region 16 and heavily-dopedsource/drain regions 18. In the shown embodiment, the LDD regions 14 areillustrated as being doped to an “n−” concentration and the source/drainregions 18 are illustrated as being doped to an “n+” concentration toindicate that the source/drain regions are more heavily doped than theLDD regions. Example relationships between n− and n+ dopantconcentrations are described in definitions provided at the end of thissection of the disclosure.

Although the illustrated transistor comprises a p-type channel, in otherembodiments the illustrated dopant types may be reversed so that thetransistor comprises an n-type channel, and comprises p-type LDD andsource/drain regions.

Gate dielectric 20 extends across the LDD regions 14 and the channelregion 16, and a gate 22 is formed over the gate dielectric. The gatedielectric may comprise any suitable composition or combination ofcompositions; and in some embodiments may comprise, consist essentiallyof, or consist of one or more of silicon dioxide, hafnium oxide,aluminum oxide, zirconium oxide, etc. The gate may comprise any suitablecomposition or combination of compositions; and in some embodiments maycomprise, consist essentially of, or consist of one or more of variousmetals (for instance, tungsten, titanium, etc.), metal-containingcompositions (for instance, metal nitride, metal silicide, metalcarbide, etc.) and conductively-doped semiconductor materials (forinstance, conductively-doped silicon, conductively-doped germanium,etc.). Although the gate dielectric is shown extending entirely acrossthe LDD regions, in other embodiments the gate dielectric may not extendacross the entirety of the LDD regions.

Contact openings 23 extend through the dielectric 20 to expose uppersurfaces of source/drain regions 18, and to provide locations forelectrical contact to the source/drain regions. In the shown embodiment,the contact openings extend entirely across the source/drain regions. Inother embodiments (not shown) one or more smaller contact openings maybe utilized to provide locations for electrical contact to thesource/drain regions. If dielectric 20 does not extend entirely acrossthe LDD regions, there may be dielectric surrounding the contact regionswhich may the same composition as the gate dielectric, or which may bedifferent in composition from the gate dielectric.

In operation, an electrical state of gate 22 determines whether the LDDregions 14 are electrically coupled to one another across channel region16. Specifically, sufficient gate voltage provides an electrical fieldwhich couples the LDD regions to one another across the channel region(i.e. the transistor is “on”), and otherwise the LDD regions are notcoupled to one another across the channel region (i.e., the transistoris “off”). Such is the normal operation of transistor 10. However, ifthere is sufficient voltage differential between a source/drain regionand the substrate or another region, then current may flow across one ormore np junctions regardless of whether the transistor is in an “on”configuration or an “off” configuration. The threshold voltagedifferential leading to such condition is referred to as a breakdownvoltage. In some applications, the breakdown voltage may correspond to abreakdown voltage between drain and source/substrate withgate/source/substrate at ground (BV_(dss))

The transistor 10 may be considered to comprise active regions 24, whichare regions of the LDD implants 14 between source/drain regions 18 andgate 22. Such active regions electrically couple the source/drainregions 18 to the channel region 16. In the shown embodiment, both ofthe active regions 24 on the opposing sides of the gate 22 have a samedopant concentration as one another. In other embodiments, such may notbe the case.

The transistor 10 has a length “L” and a width “W”. The length candetermine the breakdown voltage of the transistor, with longertransistors having higher breakdown voltages; and the width candetermine the drive current of the transistor, with wider transistorshaving higher drive currents. However, it is not simply length and widthwhich determine operational characteristics of the transistor. Forinstance, the dopant concentration within the LDD regions 14 may alsoimpact the operational characteristics of the transistor.

FIG. 3 graphically illustrates an approximate relationship betweenbreakdown voltage (BV_(dss)) and dopant concentration within LDD regions(shown on the graph as “dose”) of an example embodiment high-voltagetransistor. There is an optimum dopant concentration which achieves peakbreakdown voltage, and dopant concentrations above or below such optimumconcentration result in lower breakdown voltages. In some applications,it is desired that a high-voltage transistor operate within specifiedtolerances. A threshold breakdown voltage is shown in FIG. 3, and suchthreshold breakdown voltage may correspond to a lower end of thesuitable tolerance for a high-voltage transistor in a particularapplication. The illustrated transistor will have a breakdown voltageequal to or exceeding the threshold provided that the dopant isimplanted into an active region of the transistor at a dose within theillustrated window 28. The window 28 thus defines an operationalcharacteristic of the high-voltage transistor graphically represented inFIG. 3, in that window 28 corresponds to an implant dosage range whichwill create a transistor having a breakdown voltage within desiredtolerances.

In some embodiments, the graph of FIG. 3 may be simplified to thegraphical illustration of FIG. 4 for describing the high-voltagetransistor. Specifically, the transistor may be described simply by thedose window 28.

FIG. 5 graphically compares two different high-voltage transistors 30and 32, with the transistors being characterized by dose windows 31 and33, respectively. The transistor 30 may correspond to a relatively widetransistor having a relatively high drive current, and the transistor 32may correspond to a relatively narrow transistor having a relatively lowdrive current. The terms relatively wide and relatively narrow areutilized in relation to one another to indicate that the relatively widetransistor is wider than the relatively narrow transistor; and similarlythe terms relatively high drive current and relatively low drive currentare utilized in relation to one another to indicate that the relativelyhigh drive current is higher than the relatively low drive current. Aproblem with the transistors 30 and 32 of FIG. 5 is that the windows 31and 33 do not overlap one another, and accordingly there is no singleimplant dose which may be utilized for achieving desired breakdownvoltages of both of the transistors 30 and 32. Thus, transistor 30requires a different active area implant than transistor 32 in order tohave both of the transistors 30 and 32 formed within operationaltolerances.

FIG. 6 diagrammatically illustrates example high-voltage transistors 30and 32. Such transistors are similar to the transistor 10 of FIG. 2. Thetransistors 30 and 32 differ from one another in that transistor 30 iswider than transistor 32. Specifically, transistor 32 has a width “W₁”,and transistor 30 has a width “W₂” which is greater than “W₁”.

FIG. 7 graphically illustrates a more complicated situation than that ofFIG. 5. Specifically, FIG. 7 illustrates a configuration comprising fourtransistors 40, 42, 44 and 46, with the transistors being characterizedby dose windows 41, 43, 45 and 47, respectively. In some embodiments,the transistors may become increasingly narrow in progressing fromtransistor 40 to transistor 46. Although there is some overlap betweensome of the dose windows (for instance, dose window 41 overlaps dosewindow 43) there is no single implant dose which may be utilized forachieving desired breakdown voltages of all of the transistors 40, 42,44 and 46.

FIG. 8 diagrammatically illustrates example high-voltage transistors 40,42, 44 and 46. The transistors differ from one another in width.Specifically, transistor 46 has a width “W₃”, transistor 44 has a width“W₄”, transistor 42 has a width “W₅”, and transistor 40 has a width“W₆”; with “W₆” being greater than “W₅”, which is greater than “W₄”,which in turn is greater than “W₃”.

Some embodiments include methods of shifting dose-responsecharacteristics of relatively wide high voltage transistors so thatdesired breakdown characteristics of such relatively wide transistorsmay be achieved utilizing the same active area dopant concentrationutilized for relatively narrow transistors; and accordingly so that therelatively wide transistors and relatively narrow transistors may besimultaneously doped with a single implant. For instance, an active areaof a first transistor may be formed, and an active area of a secondtransistor may be formed. The active area of the first transistor maywider than the active area of the second transistor. Dielectric featuresmay be formed in the active area of the first transistor so that theactive area of the first transistor is broken up to a different extentthan the active area of the second transistor. The active area of thefirst transistor and the active area of the second transistor may thenbe doped with a same dopant concentration. In some embodiments, theactive areas of the first and second transistors may be simultaneouslydoped with a single implant.

FIGS. 9 and 9A show an example embodiment high-voltage transistor 50which has been modified to shift its dose-response characteristics.Similar numbering will be utilized to describe modified transistor 50 ofFIGS. 9 and 9A as is used above to describe the transistor 10 of FIGS. 2and 2A, where appropriate. Modified transistor 50 of FIGS. 9 and 9Adiffers from the transistor 10 of FIGS. 2 and 2A in that modifiedtransistor 50 has dielectric features 52 incorporated into active areas24. The features 52 may comprise any suitable dielectric material, andin some embodiments may comprise identical materials as are utilized inshallow trench isolation (for instance, may comprise one or more ofsilicon dioxide, silicon nitride, etc.) Although the illustrateddielectric features are long and thin (and specifically arerectangular), in other embodiments, the dielectric features may haveother shapes including, for example, square and/or other polygonal,circular, oval, elliptical and/or other curved, etc. Also, although allof the dielectric features 52 are shown being substantially identical toone another, in other embodiments some of the dielectric features mayhave other shapes than others of the dielectric features.

The dielectric features 52 extend through LDD regions 14, and thus breakup the active areas 24. The dielectric features shift dopant-responsecharacteristics of device 50 relative to device 10 (FIGS. 2 and 2A)while substantially maintaining drive current characteristics. In someembodiments, the shift of the dopant response characteristics may berelated to geometries and spacings of the dielectric features.Specifically, device 50 is shown to have a gate-to-contact dimension(G2C), and features 52 are shown to have lengths (L_(F)) which extendpartially across the gate-to-contact dimension. A distance from the gateto ends of the features has a gate-to-feature dimension (G2F), and adistance from ends of the features to the contact has afeature-to-contact dimension (F2C). The features have widths (W_(F)) andare spaced from one another by distances D. The amount of shift of thedopant-response characteristics of transistor 50 may be related to theratio W_(F)/D, and to L_(F); and in some embodiments may beapproximately proportional to combined effects of these twocharacteristics of the modified transistor.

The relationship of the amount of shift of dopant responsecharacteristics of modified transistor 50 to various geometrical aspectsof the modified transistor is provided to assist the reader inunderstanding this invention, and is not to limit the invention exceptto the extent, if any, that such relationship is explicitly claimed inthe claims which follow. In practice, the amount of shift ofdopant-response characteristics of a transistor modified with dielectricfeatures analogous to those shown in FIGS. 9 and 9A may be determinedthrough any suitable procedure, including, for example, through one orboth of experimentation and theoretical calculation.

Features analogous to the features 52 of FIGS. 9 and 9A may be utilizedto shift dopant response characteristics of relatively wide high-voltagetransistors so that such relatively wide transistors may be effectivelydoped with a same dopant concentration as is utilized for dopingrelatively narrow high-voltage transistors. FIG. 10 graphicallyillustrates an effect of features analogous to the features 52 of FIGS.9 and 9A, and shows two dopant response profiles 60 and 62. The profile60 shows dopant levels suitable to achieve desired breakdown voltagecharacteristics of a transistor of a given width, and profile 62 showsdopant levels suitable to achieve the same breakdown voltagecharacteristics of the same transistor after addition of featuresanalogous to the features 52 of FIGS. 9 and 9A.

An application for dielectric features analogous to the dielectricfeatures 52 of FIGS. 9 and 9A is described with reference to FIGS. 11and 12. Specifically, FIGS. 11 and 12 describe the same transistors 40,42, 44 and 46 described above with reference to FIGS. 7 and 8, but afterdopant response characteristics of transistors 40, 42 and 44 have beenmodified with dielectric features 52. The spacings and/or shapes of thedielectric features are different in the wider transistors as comparedto the narrower transistors so that all of the windows 41, 43, 45 and 47of suitable implant doses overlap one another. Accordingly, there is nowa single dose window which can be utilized for providing suitableimplant to all of the high-voltage transistor devices such that all havebreakdown voltages within desired tolerances.

FIG. 12 shows that dielectric features 52 are provided to break up theactive regions within all of the high-voltage transistors 40, 42 and 44.The amount to which the various active regions are broken up differsdepending on the widths of the transistors. For instance, transistors 42and 44 may be considered to be first and second high-voltagetransistors, respectively, having first and second active regions,respectively. The first and second active regions of the first andsecond transistors 42 and 44 are each broken up by dielectric features52, but the second active region (i.e., the narrower active region) isbroken up to a lesser extent than the first active region (i.e., thewider active region). As another example, high-voltage transistors 44and 46 may be considered to be first and second transistors,respectively having first and second active regions, respectively. Inthis case, only the first active region of transistor 44 is broken up bydielectric features 52. In some embodiments, the transistors 46, 44, 42and 40 may be considered to be first, second, third and fourthtransistors, respectively, which are increasingly wider relative to oneanother, and which have increasingly more broken up active regionsrelative to one another in order that all may have overlapping dosewindows for achieving desired breakdown voltages. In some embodiments,the dielectric features 52 within transistors 44, 42 and 40 may becomeincreasingly longer, such that L_(F1)<L_(F2)<L_(F3).

The formation of transistors 40, 42, and 44 may comprise conventionalmethodology as formation of transistor 46, with additional steps ofdetermining locations of active areas of wider high-voltage transistorswhere modification is desired to shift dopant response of thetransistors, and of making such modifications. After the appropriatemodifications are made to the wider transistors (such as addition ofdielectric features 52 or analogous dielectric features), a same activearea dopant concentration may achieve desired breakdown characteristicsof all of the transistor 40, 42, 44 and 46 (i.e., the same implant willappropriately dope wider high-voltage transistors and narrowerhigh-voltage transistors). Thus, in some embodiments an active areadopant may be simultaneously implanted into active areas of all of thehigh-voltage transistors 40, 42, 44 and 46 to achieve desired breakdowncharacteristics of all of the transistors.

The illustrated modified transistors of FIGS. 9 and 12 have thedielectric features 52 uniformly distributed on both sides of gate 22 sothat the dielectric features on one side of the gate are a mirror imageof the dielectric features on the other side of the gate. In otherembodiments, the dielectric features may be asymmetrically distributedrelative to the gate. For instance, in some embodiments one of thesource/drain regions 18 carries high-voltage in an off-state of thetransistor device, and the other does not. For instance, one of thesource/drain regions may be a drain region which carries high-voltage inan off-state and the other may be a source region which does not carryhigh high-voltage in the off-state. In such embodiments, the dielectricfeatures 52 may be arranged to be primarily between the gate and thesource/drain region which carries high-voltage in an off-state of thetransistor device. FIG. 13 shows an example embodiment high-voltagetransistor 80 having a source region 82 and a drain region 84, andhaving the dielectric features 52 within the active region between thegate 22 and the drain region 84, and not within the active regionbetween the gate 22 and the source region 82. In other embodiments,there may be some dielectric features between the gate 22 and the sourceregion 82, but fewer than between the gate 22 and the drain region 84.

The high-voltage transistors described herein may be utilized inintegrated circuitry, and in some embodiments may be utilized forcontrolling electrical flow to logic and/or memory. For instance, insome embodiments the high-voltage transistors may be electricallycoupled to a flash memory array (for instance, a NAND array) andutilized for controlling electrical flow during block erase operationsof the flash memory and/or other programming operations of the flashmemory.

Although dielectric features are shown in the accompanying figures asbeing utilized in high-voltage transistors, in some embodimentsanalogous dielectric features may be utilized in other transistors,which may or may not be high voltage transistors.

The electronic devices described herein may be incorporated intoelectronic systems. Such electronic systems may be used in, for example,memory modules, device drivers, power modules, communication modems,processor modules, and application-specific modules, and may includemultilayer, multichip modules. The electronic systems may be any of abroad range of systems, such as, for example, clocks, televisions, cellphones, personal computers, automobiles, industrial control systems,aircraft, etc.

The terms “dielectric” and “electrically insulative” are both utilizedto describe materials having insulative electrical properties. Bothterms are considered synonymous in this disclosure. The utilization ofthe term “dielectric” in some instances, and the term “electricallyinsulative” in other instances, is to provide language variation withinthis disclosure to simplify antecedent basis within the claims thatfollow, and is not utilized to indicate any significant chemical orelectrical differences.

The particular orientation of the various embodiments in the drawings isfor illustrative purposes only, and the embodiments may be rotatedrelative to the shown orientations in some applications. The descriptionprovided herein, and the claims that follow, pertain to any structuresthat have the described relationships between various features,regardless of whether the structures are in the particular orientationof the drawings, or are rotated relative to such orientation.

The cross-sectional views of the accompanying illustrations only showfeatures within the planes of the cross-sections, and do not showmaterials behind the planes of the cross-sections in order to simplifythe drawings.

When a structure is referred to above as being “on” or “against” anotherstructure, it can be directly on the other structure or interveningstructures may also be present. In contrast, when a structure isreferred to as being “directly on” or “directly against” anotherstructure, there are no intervening structures present. When a structureis referred to as being “connected” or “coupled” to another structure,it can be directly connected or coupled to the other structure, orintervening structures may be present. In contrast, when a structure isreferred to as being “directly connected” or “directly coupled” toanother structure, there are no intervening structures present.

Some of the figures show various different dopant levels, and utilizesome or all of the designations p+, p, p−, n−, n and n+ to distinguishthe levels. The difference in dopant concentration between the regionsidentified as being p+, p, and p− are typically as follows. A p+ regionhas a dopant concentration of at least about 10 ²⁰ atoms/cm³, a p regionhas a dopant concentration of from about 10 ¹⁴ to about 10 ¹⁸ atoms/cm³,and a p− region has a dopant concentration in the order of or less than10 ¹⁶ atoms/cm³. It is noted that regions identified as being n−, n andn+ will have dopant concentrations similar to those described aboverelative to the p−, p and p+ regions respectively, except, of course,the n regions will have an opposite-type conductivity enhancing dopanttherein than do the p regions. It is noted that the terms “p” and “n”can be utilized herein to refer to both dopant type and relative dopantconcentrations. The terms “p” and “n” are to be understood as referringonly to dopant type, and not to a relative dopant concentration, exceptwhen it is explicitly stated that the terms refer to relative dopantconcentrations. Accordingly, for purposes of interpreting thisdisclosure and the claims that follow, it is to be understood that theterm “p-type doped” and “n-type doped” refer to dopant types of a regionand not to relative dopant levels. Thus, a p-type doped region can bedoped to any of the p+, p, and p− dopant levels discussed above, andsimilarly an n-type doped region can be doped to any of the n+, n, andn− dopant levels discussed above.

Some embodiments include integrated circuits having first and secondtransistors. The first transistor is wider than the second transistor.The first and second transistors have first and second active regions,respectively. Dielectric features are associated with the first activeregion and break up the first active region. The second active region isnot broken up to the same extent as the first active region.

Some embodiments include methods of forming transistors of differentwidths. An active area of a first transistor is formed. An active areaof a second transistor is formed, where the active area of the firsttransistor is wider than the active area of the second transistor.Dielectric features are formed in the active area of the firsttransistor, where the active area of the first transistor is broken upto a different extent than the active area of the second transistor. Theactive area of the first transistor and the active area of the secondtransistor are doped with a same dopant concentration.

Some embodiments include methods of forming transistors of differentwidths. An active area of a first transistor is formed. An active areaof a second transistor is formed, where the active area of the firsttransistor is wider than the active area of the second transistor.Dielectric features are formed in the active area of the firsttransistor, where the active area of the first transistor is broken upto a different extent than the active area of the second transistor. Theactive area of the first transistor and the active area of the secondtransistor are simultaneously doped with a single implant.

In compliance with the statute, the subject matter disclosed herein hasbeen described in language more or less specific as to structural andmethodical features. It is to be understood, however, that the claimsare not limited to the specific features shown and described, since themeans herein disclosed comprise example embodiments. The claims are thusto be afforded full scope as literally worded, and to be appropriatelyinterpreted in accordance with the doctrine of equivalents.

1-22. (canceled)
 23. A transistor comprising: a gate comprising a firstside opposite a second side; a drain region spaced from the first sideof the gate; a source region spaced from the second side of the gate;and at least one dielectric feature between the gate and one of thesource and drain regions.
 24. The transistor of claim 23 furthercomprising active regions adjacent the opposites sides of the gate, theactive regions comprising the same dopant concentration.
 25. Thetransistor of claim 23 wherein the other of the one of the source anddrain regions has no dielectric features.
 26. The transistor of claim 23wherein the at least one dielectric feature comprises two or moredielectric features.
 27. The transistor of claim 23 wherein the at leastone dielectric feature comprises at least three dielectric features. 28.The transistor of claim 23 comprising a high-voltage transistor.
 29. Thetransistor of claim 23 wherein the at least one dielectric feature islocated between the gate and the source region.
 30. The transistor ofclaim 23 wherein the at least one dielectric feature is located betweenthe gate and the drain region.
 31. The transistor of claim 23electrically coupled to a flash memory array.
 32. The transistor ofclaim 23 electrically coupled to a NAND array.
 33. The transistor ofclaim 23 further comprising active regions adjacent the opposites sidesof the gate, the active regions comprising lightly-doped diffusionregions.
 34. The transistor of claim 23 wherein the at least onedielectric feature comprises a plurality of dielectric features, theplurality of the dielectric features are spaced along the widthdirection of the transistor.
 35. The transistor of claim 23 wherein theat least one dielectric feature comprises at least two dielectricfeatures spaced along the width direction of the transistor.
 36. Thetransistor of claim 23 wherein the at least one dielectric featurecomprises at least three dielectric features spaced along the widthdirection of the transistor.
 37. The transistor of claim 23 wherein theone of the source and drain regions is configured to carry high-voltagein an off-state of the transistor.